1. Field of the Invention
This invention relates to an integrated circuit, no-delay AND gate compatible with a four-phase, major-minor metal oxide semiconductor (MOS) system.
2. Prior Art
A type 1 inverter gate (which evaluates during a .phi..sub.1 multi-phase clock signal) and a type 4 inverter gate (which evaluates during a .phi..sub.4 multi-phase clock signal) are shown and described in U.S. Ser. No. 659,057 filed Feb. 18, 1976, and now abandoned. It is known to those skilled in the art that the output signal from a type 1 inverter gate can be applied to the input of a type 2 inverter gate (which evaluates during the .phi..sub.2 multi-phase clock signal). It is also known that the output signal from a type 4 inverter gate can be applied to the input of a type 2 inverter gate. However, no efficient gating means is known by which to concurrently fan the output signals from both the type 1 and 4 inverter gates into the type 2 inverter gate without the utilization of complex interface logic, inasmuch as no controllable time interval is available in a conventional four-phase clocking scheme to permit the fan-in to occur.
Prior art attempts to resolve the problem of fanning the type 1 and 4 inverter gates into a type 2 inverter gate have included interface gating means such as d.c. inverters, amplifiers or the like. However, the prior art attempt to employ interface gating means results in an undesirable gating time delay, as well as d.c. power loss, increased space consumption and uneconomical costs.